Understanding the Ethernet Nomenclature – Data Rates, Interconnect Mediums and Physical Layer. 6. The minimum IPG “observed” at the MAC would always be 12. 2. 125 GHz Serial IEEE standard USGMII 8x ≤1 Gbit/s 1 Lane 4 10. 25 Mbps. , 3G) • Somewhere in PCS, data rate must be adapted between fixed MAC rate (10G) and effective PMD data rate (3G) • Adaptation process may rely on removal of excess IDLE characters inserted by MACClause 46 uses the term column when describing data transfers on the XGMII. This design offers the following features: Loopback points that include XGMII and serial physical medium attachment (PMA) interface in the Arria® 10 FPGA development board, and PMA interface in the Broadcom PHY BCM8727 chip on the Dual XAUI to SFP+ HSMC board. This. The 16-bit TX and RX GMII supports 1GbE and 2. rst)10 ギガビット イーサネット PCS/PMA (10GBASE-R) は、10 ギガビット イーサネット MAC への接続に XGMII インターフェイスを提供し、10. 2. By: Rita Horner, Senior Technical Marketing Manager, Synopsys. 3. Simulating Intel® FPGA IP. Register Map 7. 2. The MAC TX also supports custom preamble in 10G operations. NBASE-T Alliance 白 1 概述 十年来，企业网络访问层的配备已能满足其大部分 1000BASE-T 以 太网的吞吐量需求，但这项全能技术已经濒临淘汰。Which looks remarkably similar to how the XGMII encoding looks, but its not. The Synopsys Ethernet QoS 5. System battery specifications. TX data from the MAC. 3-2008, defines the 32-bit data and 4-bit wide control character. Core data width is the width of the data path connected to the USXGMII IP. 3125 Gb/s link. 每條信道都有. Configuration Registers x. The XGMII design is now provided with the 10-Gig MAC Core in CORE Generator. In contrast, the XLGMII/CGMII interfaces are intended only for use on-chip, and are defined differently as SDR interfaces, see 802. XGMII Mapping to Standard SDR XGMII Data. Two XGMII data transfers are decoded from each block. 125 GHz Serial IEEE standard USGMII 8x ≤1 Gbit/s 1 Lane 4 10. Common signals. 5GPII Word encoder/decoder –mapping between XGMII to Internal 2. The average IPG is maintained at 96 bit times (12 byte times) using the deficit idle count (DIC). 5G/5G/10G. A8. 3 2. To use these modules, import the one you need and connect it to the DUT: from cocotbext. 1. 6. The effective XGMII data is running at 156. await xgmii_source. This is most critical for high density switches and PHY. XGMII Mapping to Standard SDR XGMII Data. Thus: For each Ethernet supported device you will have Either SGMII, RGMII interfaces for the data stream. 數據接口包括分別用於發送器和接收器的兩條獨立信道。. 7. The switch is capable of auto-negotiating with SGMII and 1000BaseX connections and by default set to SGMII. 10 Gigabit Attachment Unit Interface ( XAUI / ˈzaʊi / ZOW-ee) is a standard for extending the XGMII (10 Gigabit Media Independent Interface) between the MAC and PHY layer of 10 Gigabit Ethernet (10GbE) defined in Clause 47 of the IEEE 802. A tag already exists with the provided branch name. cancel. 0 5 Network Controller Sideband Interface (NC-SI) 6 Specification 7 Document Type: Specification 8 Document Status: DMTF Standard 9 Document Language: EI read ethernet 1000base user guide but that is not clear for me what is difference between SGMII and ethernet 1000base? In their definition was written : Ethernet 1000base : The IEEE802. 17. The DPL blob is put at 0x80d00000 by default, but then overwritten by kernel which is put at 0x80080000 (default for the FIT image produced by Yocto). Hi, The critical warning message is just that, nothing more. The 1080p Xgimi Elfin delivers film and video quality easily suitable for casual viewing, and adds surprisingly high brightness for a projector that weighs all of two pounds. The core was released as part of Xenie FPGA module project. Product Family: Application Tooling. USXGMII subsystem with DMA to ZynqMP system running Linux. There is some translation of control characters as it goes on to the physical interface (serdes) so as to maintain synchronization and alignment of lanes. The minimum IPG observed at the XGMII would “dither” between 9 and 15 bytes, but would average 12. Figure 49–4 depicts the relationship and mapping Media Independent Interface ( MII )，介质独立接口，起初是定义100M以太网（Fast Ethernet）的 MAC 层与 PHY 芯片之间的传输标准（802. April 20, 2022 at 4:15 PM. Xenie module is a HW platform equipped with. Regards, Pat -----Original Message----- From: Justin Gaither [mailto:jgaither@xxxxxxxxxxxxxxx] Sent: Wednesday, February 14, 2001 11:29 AM To:. The 1G/10G switch supports MAC learning, VLAN 802. The 1G/2. Related Information • Introduction to Intel FPGA IP Cores Provides general information about all Intel FPGA IP cores, includingXGMII Ethernet Verification IP. 7. • XAUI Extender: This block is an XGMII extender to support the XAUI protocol through a FPGA IP MAC core in the FPGA fabric. 做回环测试时，在AXI数据发送前，GT口就有一些数据，请问这些是什么数据？. Like Liked Unlike Reply. It looks like all of the latest 10GE IP from Xilinx no longer has an MDIO to interface to external PHYs. The tcpIpPg project is a set of verification IP for generating and receiving 10GbE TCP/IPv4 Ethernet packets over an XGMII interface in a Verilog test environment. Due to the continuously signaled nature of the underlying PMA, and the encoding performed by the PCS, the 10GBASE-X PCS maps XGMII data and control characters into a code-group. They call this feature AQRate. 3. Utilization of the Ethernet protocol for connectivity is widespread in a broad range of things or devices around us. Behavior of the MAC TX in custom preamble mode: PCS service interface is the XGMII defined in Clause 46. 6. •. • Single 10G and 100M/1G MACs. 0 3 3 A Managed Switch System A managed switch system is composed of at least an Ethernet switch chip, several physical layer devicesThe core is aimed to be used for 10 G Ethernet in both optic and metallic version (64bit XGMII internal interface). For PHYs that support EEE capability, CARRIER_STATUS is set in response to LPI. XGMII and to reduce the number of interface signals. 1Q, and multicast. • /T/-Maps to XGMII terminate control character. Additionally, for applications requiring 20 Gbps throughput, Intel FPGA's XAUI PHY solution can support DXAUI (4 x 6. The Synopsys Ethernet QoS 5. png However I do have a followup question to this. CTRL is inserted. 3. 49. The Reconciliation Sublayer provides a mapping between the signals provided at the XGMII and the MAC/PLS service definition. LS1043ARDB Ethernet and FMC port mapping. Storage controller specifications. Several Physical Coding Sublayers known as 10GBASE-X, 10GBASE-R, and10GBASE-W are specified, as well as significant additional supporting material for a 10 GigabitMedia Independent Interface (XGMII), a 10 Gigabit Attachment. 10GbE XGMII TCP/IPv4 packet generator for Verilog. Definitely not XGMII (32-bit DDR, was never really seen off-chip) or XAUI (4 lanes of 3. Memory specifications. 46 - XGMII Optional 47 – XGXSand XAUI Optional 48 – 10GBASE-X PCS/PMA Required The XGMII is an optional interface. The 10 Gigabit Media Independent Interface (XGMII) is an interface standard that uses 72 data pins for both RX and TX. 1. The MAC RX expects the first byte of receive packets to be in lane 0, xgmii_rx_data [7:0]. 3 Mapping of PLS_CARRIER. Altera offers two Ethernet MAC IP cores that can support up to 10 Gbps speed mode—10-Gbps Ethernet (10GbE) Media Access Controller (MAC) IP core and Low Latency Ethernet 10G MAC IP cores. 5Gb/s, 5Gb/s, and 10Gb/s Physical Coding Sublayers (PCS) are specified to the XGMII, so if not implemented, a conforming implementation shall behave functionally as if the RS and XGMII were implemented. Operation at 10 Mb/s and 100 Mb/s is supported by the MII defined in Clause 22 and operation at 1000 Mb/s by the GMII defined in Clause 35. About the F-Tile 1G/2. While XGMII provides a 10 Gb/s pipeline, the separate transmission of clock and data coupled with the timing requirement to latch data on both the rising and falling edges of the clock results in significant challenge in routing the bus more than the recommended short distance of 7 cm. 4. 3125Gbps to. BOOT AND CONFIGURATION. PROGRAMMABLE LOGIC, I/O AND PACKAGING. First, when I use default DIP setting from user guide (boot from SD) Boot source. 3ae 10 Gigabit Ethernet 10 Gigabit Media Independent Interface n 32 data bits, 4 control bits, one clock, for transmit n 32 data bits, 4 control bits, one clock, for receive n Dual Data Rate (DDR) signaling, with data and control driven and sampled on both rising edge and falling edge of clock USXGMII. 4 core product guide only lists SGMII LVDS support for Virtex-7 and Kintex-7 devices. 17. 16. The VSC8486 is a LAN/WAN XAUI or XGMII transceiver that converts 3G XAUI data to a 10G serial stream. This driver includes support for the following Synopsys (R) DesignWare (R) Cores Ethernet Controllers and corresponding minimum and maximum versions: For questions related to hardware requirements, refer to the documentation supplied with your Ethernet adapter. Comcores Ethernet Switch 10G IP core is a highly configurable and size-optimized implementation of a non-blocking switch that allows continuous transmissions between up to 16 10G Ethernet ports. 5G/1G Multi-Speed Ethernet MACThe 64B/66B encoder is used to achieve DC-balance and sufficient data transitions for clock recovery. v","path":"rtl/arp. xgmii_rx_dc[71:0&rbrack. It is easier to just create this in HSI. Section Content. Virtually Install CentOS and Fedora on Zynq UltraScale+. 20. D. USGMII supports eight 10M/100M/1G network ports over 10Gbps SERDES between MAC and PHY. 1. You can do the high-speed parallel parts in the FPGA fabric and do higher-level processing on the built-in CPU. v","path":"rtl/arp. 25 MHz interfacing with the MAC layer. Microsemi's 10GE PHY portfolio is highly flexible, covering a broad range of port speeds and interface types. Serdes Lane A is connected to a Broadcom Ethernet switch on the board via SGMII. Uses 7 series, Virtex 6, Virtex 5, Virtex 4, and Spartan 6 transceivers running 4 lanes at 3. The 10 Gigabit Media Independent Interface ( XGMII) is an interface standard that uses 72 data pins for both RX and TX. 1. Designed to meet the USXGMII specification EDCS-1467841 revision 1. 7xxx/5xxx SoCs), SPEAr (arm), Loongson1B (mips) and XILINX XC2V3000 FF1152AMT0221 D1215994A VIRTEX FPGA board. => setenv serverip <ipaddress1> Set ethact and ethprime as the ethernet interface connected to the. 设计符合 IEEE 802. IEEE 802. nsy_0415@hotmail. Currently, this network device driver is for all STi embedded MAC/GMAC (i. OTHER INTERFACE & WIRELESS IP. XGMII XGMII PHY FEC Reconciliation 10GBASE-X PCS 10GBASE-X PCS PCS PMA PMD Medium MDI XAUI XGMII XGMII PHY These sublayers are upside down As previous page, right hand side FEC 10GBASE-X PMA 10GBASE-X PMA XGMII MAC MAC Chip-to-chip "extender", possibly one connector Medium X PMA X PMA FIFOs, crystal Drawn right. 它是IEEE-802. 5. Experience unforgettable entertainment with products like the 4K XGIMI HORIZON Pro, ultra-portable XGIMI Halo+, or our new laser projector XGIMI AURA. 3 protocol and MAC specification to an operating speedof 10 Gb/s. I am checking if there might be some lack of robustness with this scheme. control, combines themIII. 8 Author Yi-Chin Chu Project Manager JR Rivers Serial-GMII Specification The Serial Gigabit Media Independent Interface (SGMII) is designed to satisfy the followingOn the user side a pair of AXI4-Stream (one master and one slave) interfaces are used to send and receive Ethernet frames from/to the user logic. 2. Loading Application. Native PHY IP Ports for 10GBASE-R and 10GBASE-R. Media-independent interface#XGMII To a section : This is a redirect from a topic that does not have its own page to a section of a page on the subject. 2 mac层. 2. But the chipscope indicates that xgmii_txd are. {"payload":{"allShortcutsEnabled":false,"fileTree":{"rtl":{"items":[{"name":"arp. 3 designed for connecting full duplex 10 Gigabit Ethernet (10GbE) ports to each other and to other electronic devices on a printed circuit board (PCB). XGMII to XAUI conversion The TLK3134, known as a XGXS or XGMII extender, converts the 74 wires required by XGMII to 16 wires, which is a more manageable interface known as XAUI. // Documentation Portal . AVST-XGMII – monitor the packet condition at client Avalon-ST and XGMII interface a. 4. 2. SW1 [1:8]RGMII (Reduced Gigabit Media Independent Interface) 존재하지 않는 이미지입니다. The Alaska® F and Alaska G families of Fast Ethernet and Gigabit Ethernet physical layer (PHY) transceivers are built on Marvell’s legacy of unique, best-in-class features that enable customers to expand their Ethernet applications. 8. SERIAL TRANSCEIVER. The system data width, that is, the width of the interface to the user logic, is c onfigured as 64 bits. The 10G USXGMII Ethernet design example demonstrates the functionalities of the LL 10GbE MAC Intel® FPGA IP core operating at 10M, 100M, 1G, 2. MAC – PHY XLGMII or CGMII Interface. • Data Capture: Record data packets in-line between twoSystem dimensions. ! If connected to WAN PMD, inserts/deletes idles due to rate difference between MAC and PMD! Determines when link available, therefore informing management entity via MDIO when PHY is ready to be used. It supports 10M/100M/1G/2. 18. These characters are clocked between the MAC/RS and the PCS at both the positive and negative edge (double data rate – DDR) of the 156. Core data width is the width of the data path connected to the USXGMII IP. Due to the continuously signaled nature of the underlying PMA, and the encoding performed by the PCS, the 10GBASE-X PCS maps XGMII data and control characters into a code-group. 3 media access control (MAC) and reconciliation sublayer (RS). PHY is the physical media you attach to (Cat5/6 cable, or fiber, or WiFi). 6. However, by running the example design simulation of the 10/25G IP I did find that the preamble and SFD octets are indeed included: ethernet_preamble. RSはMACのシリアルデータ列をXGMIIのパラレルデータパスに変換する。 The XGMII interface, specified by IEEE 802. It encodes 64-bit XGMII data and 8-bit XGMII control into 10GBASE-R 66-bit control or data blocks in accordance with Clause 49 of the IEEE802. We are using the 10G/25G Ethernet Subsystem for 10G with PCS only. The design in CORE Generator contains necessary updates for Virtex-II and later devices. The full spec is defined in IEEE 802. Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines. 4/2. IEEE 802. Microsemi's 10GE PHY portfolio is highly flexible, covering a broad range of port speeds and interface types. Remember the XGMII encoding is 1bit of control (0b -> data, 1b -> control) for every 8bits of data. QSGMII Specification: EDCS-540123 Revision 1. . 允许在 7 系列、Virtex 6、Virtex 5、Virtex 4 FX、Virtex II Pro 或 Spartan 6 FPGA 与行业标准. e. The 10 Gigabit Media Independent Interface (XGMII) version of this core is intended to interface to either an off-chip PHY device or XAUI, DXAUI, RXAUI, 10GBASE-R/KR LogiCORE using the XGMII Interface. Implements DTE XGXS, PHY XGXS and 10G BASE-X PCS in a single netlist. 2. 3z Task Force 3 of 12 11-November-1996 microsystems Source Synchronous Clocking Concept: Implementation I Timing: Cycle Time = [Tcq + dTdr] + [dTbrd] + [dTrcv + Tis] + [Trsk] Tcq is the clock to Q delay; dTdr, dTbrd and dTrcv are the timing skews for driver, board and receiver; Tis is the Input Setup time; Trsk is the clock risetime skew. This PHY IP core is made available as part of the transceiver functionality of the Intel® FPGAs. 10 gigabit media-independent interface (XGMII) is a standard defined in IEEE 802. Networking. Implements DTE XGXS, PHY XGXS and 10G BASE-X PCS in a single netlist. Supports PHY interfaces of XGMII (32/64-bits) at 312. This block. IEEE 802. When the 10-Gigabit Ethernet MAC Core was released back in 2001, the original implementation of the XGMII was as per XAPP606. XAUI. 8. • Synchronization of code groups on each lane to determine code group boundaries • Deskew of received code groups from all lanes toXGMII Signals 6. Interface Signals 7. The XCM . Due to the continuously signaled nature of the underlying PMA, and the encoding performed by the PCS, the 10GBASE-X PCS maps XGMII data and control characters into a code-group stream. This greatly reduces. Generate the design example from the Example Design tab of the LL 10GbE Intel® FPGA IP parameter editor. 10G/25G Ethernet Subsystem example仿真GT口的问题. The XAUI core is an extension of the XGMII interface and as such there is no data-stripping happening within the core. Leverages DDR I/O primitives for the optional XGMII interface. 万兆位以太网 pcs/pma (10gbase-r) 是一款免费 logicore™，不仅可为万兆位以太网 mac 提供一个 xgmii 接口，而且还可实现 10. 2. Historically, Ethernet has been used in local area networks (LANs. 14. 1. DATA is generated. Male and Female Crimp Terminals, 16 AWG. . Most Ethernet systems are made up of a number of building blocks. The Intel® Stratix® 10 devices contain a combination of GX, GXT, or GXE channels, in addition to the. You will need to compile this. Email This Page. Technology and Support. 3 の第 49 項で定義されている BASE-R PCS/PHY (Physical Coding Sublayer/Physical Layer) を採用し、10M、100M、1G、2. 2. PCS B. The MAC TX also supports custom preamble in 10G operations. 1, 2. Overview. • 3) Allow variation in the minimum IPG at the XGMII – Allow packets to be held back until the next lane 0 alignment, and make up by shrinking a subsequent IPG. products. Introduction to Intel® FPGA IP Cores 2. System battery specifications. 19. 3125 Gbps のシリアル シングル チャネルの PHY をインプリメントして、XFI 電気的仕様を使用した XFP への直接接続や、SFI 電気的仕様を使用した SFP+ オプティカル. 7. USXGMII specification EDCS-1467841 revision 1. 5x faster (modified) 2. v","contentType":"file"},{"name":"arp_cache. 3 Clause 46 but we will save you the legalize parse time and explain it in pl Optional XGMII Extender XGMII 10 Gigabit Media Independent Interface 32 data (4 ‘lanes’ of 8 bits), 4 control and 1 DDR clock Medium XGMII XAUI XGMII XAUI 10 Gb/s Attachment Unit Interface 4 serial lanes @ 2. References 7. It utilizes built-in transceivers to implement the XAUI protocol in a single device. v","path":"rtl/arp. These characters are clocked between the MAC/RS and the PCS at both the positive and negative edge (double datarate – DDR) of the 156. Supports 10M, 100M, 1G, 2. XGMII (64-bit data, 8-bit control, single clock-edge interface). 5. 1: The values of TXC<7:0> and TXD<63:0> shall be sampled by the PHY on the rising edge of TX_CLK. PCS Registers 5. Transceiver Status and Transceiver Clock Status Signals 6. It's exactly the same as the interface to a 10GBASE-R optical module. The name is a concatenation of the Roman numeral X, meaning ten, and the initials of. 1G/10GbE Control and Status Interfaces 5. I connect RX to TX directly in the real test. Overview. MII Interface Signals 5. XGMII interleaver for interfacing with PHY cores that interleave the control and data lines. 14. As Linux is running on the ARM system, a specific IMX547 driver is used. 它是IEEE-802. Version 1. 5GPII Word encoder/decoder –mapping between XGMII to Internal 2. XGMII Conversion, XGMII to GMII conversion, and arbi-trator module. Dear all I read pg251 and pg210 in order to choose the best solution between usxgmii (Universal Serial XGMII Ethernet Subsystem) or xxv_ethernet (10G/25G Ethernet Subsystem) for using in a standard 10G Ethernet system using the SFP modules of the ZCU106 Xilinx board (described below). Angstrom on Zynq UltraScale+. When asserted, indicates the start of a new frame from the MAC. 5GPII Word • 3) Allow variation in the minimum IPG at the XGMII – Allow packets to be held back until the next lane 0 alignment, and make up by shrinking a subsequent IPG. The standard XLGMII or CGMII implementation consists of 32 bit wide data bus. XGMII Transmission. Processor specifications. The full spec is defined in IEEE 802. 1858. 6. PRESENTATION. Installing and Licensing Intel® FPGA IP Cores 2. If the 32-bit/64-bit adapter on the XGMII is present, the first byte of receive packets must. PCS service interface is the XGMII defined in Clause 46. 0: Disables USXGMII Auto-Negotiation and manually configures the operating speed with the USXGMII_SPEED register. 25 MHz Double Data Rate (DDR), parallel, short-reach interconnect interface. 1. The 2. A separate APB interface allows the host applications to configure the Controller IP for Automotive. VIVADO. Microsemi's latest generation 10GE PHYs feature VeriTime™, Microsemi's patent pending timing. There is no real PHY device involved here, the LS1043A Serdes is directly connected to the switch Serdes. The. 3bz standard is similar, but leaves physical implementations of the PHY-MAC interface . clk, dut. Lane 0 starts from the least significant bit. PMA Registers 5. Read clock. 10GBASE-X andInterface (XGMII)) Change 46. Therefore, for 2. 1. Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type. However, the bus widths of the xgmii interfaces on the MAC and XAUI do not match. To use custom preamble, set the tx_preamble_control. 6. AMDGPU XGMI Support. 5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP core implements USXGMII PCS based on Cisco specification. bin to flash ethernet-phy firmware (aq_programming_atf_lsdk1906. It can work with SystemVerilog,Vera, SystemC, E and Verilog HDL environment. e. 4. 4. When the MAC RX receives a local fault, the MAC TX starts sending remote fault status (0x0200009c) on the XGMII. The inclusion of a XGMII means that several alternative PHY interfaces are readily supported, including XSBI (10 Gigabit Sixteen Bit Interface) and XAUI. Starting with CDNA 3, AMD claims it will deliver more than a. @allanherrimanan. IP应用. TLK3134 supports a 32-bit data path, 4-bit control, 10 Gigabit Media Independent Interface (XGMII) to the protocol device. 7 by 4. SWAP C. SoCKit/ Cyclone V FPGA A. Creating Devicetree from Devicetree Generator for Zynq Ultrascale and Zynq 7000. 5G/5G/10G (USXGMII). MII即媒體獨立接口，也叫介質無關接口。. Serial Data Interface 5. PCS service interface is the XGMII defined in Clause 46. 5 Gbps, 1 Gbps, 100 Mbps, 10 Mbps. Storage controller specifications. 3 Clause 46 but we will save you the legalize parse time and explain it in plain English. 2. This driver includes support for the following Synopsys (R) DesignWare (R) Cores Ethernet Controllers and corresponding minimum and maximum versions: For questions related to hardware requirements, refer to the documentation supplied with your Ethernet adapter. 5. The XgmiiSink receives XGMII traffic, including monitoring internal interfaces. 3 Overview. 5G and 10G BASE-T Ethernet products. The transceivers do not support the XGMII interface to the MAC/RS as defined in the IEEE 802. 4 11/18 Microsemi Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 XGMII Update Page 4 of 12 hmf 11-July-2000 IEEE 802. 5G, 5G, or 10GE data rates over a 10. 4. Performs endian conversion. The Existing Axi Ethernet driver in the Xilinx git hub supports 1588 for 1G MAC and legacy 10G MAC and 10G/25G MAC. 25MHz clocking (no additional transceiver control and status ports) Shared logic included in example design No MDIO Management features Best regards, Dave G. The LVDS I/Os in the Intel® Stratix® 10, Intel® Arria® 10, Stratix® V, Stratix® IV, Stratix® III, Arria® V, Arria® II GX (fast speed grade), Intel® Cyclone® 10 GX and LP FPGAs allow you to easily implement the Serial Gigabit Media Independent Interface (SGMII) for 10/100/1000 Mb or Gigabit. 14. The XGMII interface, specified by IEEE 802. (MAC) core, which can be configured in XGMII and 10GBASE-R modes. XGMII Decapsulation. The XGMII design is now provided with the 10-Gig MAC Core in CORE Generator. Optional 802. LAN の主流であるイーサネットで初めて WAN での利用を前提とした技術を含む [1] 。. It supports 10M/100M/1G/2. PROGRAMMABLE LOGIC, I/O AND PACKAGING.